The invention relates to tape automated bonding.
Tape automated bonding (TAB) is an interconnection system which is used to connect semiconductor chips (die) to a next level of interconnection (e.g., a printed circuit (PC) board or an integrated circuit package). TAB uses a TAB tape having a substrate which defines sprocket holes and windows, and a plurality of conductors, which are arranged in frames of interconnect patterns superimposed over the substrate. Each frame's conductors extend over a respective window. An integrated circuit (IC) die is inserted into the window from below the die and the inputs and outputs (I/O's) of the TAB tape are bonded to the ends of the conductors which extend over the window. The conductors with ICs attached are then severed from the TAB tape and simultaneously attached to a PC board, e.g., via surface mounting technology.
Conventional TAB tape is fabricated by registering a mask containing a desired conducting portion pattern over a tape having a layer of photoresist superimposed over a layer of conducting material, exposing a section of the photoresist layer of tape through the mask to high energy electromagnetic radiation, advancing the tape a set amount, stopping the tape, and exposing another section of the tape. As subsequent sections of tape are exposed, the photoresist layer of previous sections are developed to define patterns of conductive portions which are used to etch the layer of conducting material to provide frames of conductors arranged in interconnect patterns on the surface of the tape.
An alternative to TAB is wire bonding in which individual wires are bonded between the IC die's inputs and outputs and the PC board. TAB provides a plurality of widely acknowledged advantages which include: higher functional board density and reduction in printed circuit (PC) board real estate; lower assembly costs in volume runs; decreased material costs as TAB requires substantially less conductive material; more mechanical reliability; better performance because the short length of TAB leads decreases the wiring length between the IC die and the next level of interconnection; and, better heat dissipation because the back of the IC die can be directly attached to heat sinks. Additionally, because the IC die is bonded to conductive portions which are supported by the tape, TAB technology improves quality control by allowing each IC die to be electrically tested and burned-in prior to any board level assembly. See Banks, "Facts about TAB", Printed Circuit Assembly, Vol. 3, No. 3 (March 1989), pp. 28-30, and Castrovilla, "Surface Mount and TAB: Their Impact on PWBs", Printed Circuit Assembly, Vol. 3, No. 3 (March 1989), pp. 35-37.
Despite TAB's widely acknowledged advantages, the present technology of TAB presents a number of limitations. Presently, the TAB process is only used to produce a tape having a succession of identical chip interconnection patterns because TAB is presently fabricated using a mask which must be aligned with the unexposed TAB tape. The semiconductor industry, however, is currently shifting from standardized chip designs to application specific integrated circuits (ASIC). ASICs are integrated circuits which are designed for a particular application, thus, ASICs provide a user with the advantage of reducing the chip count in a particular design. The number of ASIC designs is increasing, and, along with this increase, the number of different chip interconnection patterns is also increasing. Accordingly, the TAB technology must also shift "from high volume, long-run, reel-to-reel commodity chip patterns to low-volume, short-run, singulated ASIC patterns." Augelucci, Sr., "The state of TAB interconnects", Electronic Engineering Times, Issue 555 (Sep. 11, 1989), p. T12.
Added to this limitation is the increasing use of Just-In-Time Inventory Control in which a subassembly is completed just as it is needed for the next level of integration. The present TAB technology is antithetical to the just-in-time philosophy because TAB in its present form is only efficient for use in generating long runs of the same chip interconnection pattern.
An additional limitation arises in using TAB technology in developing new or unique systems such as prototypes. The non-recurring engineering costs such as design engineering and photo-tooling of the present TAB technology can be both prohibitively expensive and time consuming when used in a Low volume application such as a prototype system.